State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

DEVELOPING VARIATION AWARE SIMULATION TOOLS, MODELS, AND DESIGNS FOR STT-RAM by

STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement

High capacity Last Level Cache (LLC) architectures have been proposed to mitigate the widening processor-memory speed gap. These LLC architectures have been realized using DRAM or SpinTransfer-Torque Random Access Memory (STT-RAM) memory technologies. It has been shown that STT-RAM LLC provides improved energy efficiency compared to DRAM LLC. However, existing STT-RAM LLC suffers from increased...

Using STT-RAM Based Buffers in Digital Circuits

STT-RAMs are good candidates to replace conventional SRAM cache and DRAM in main memory, but their applicability in digital logic circuits is unclear. Our experiments explore the power benefit of utilizing nonvolatile buffers in digital circuits, with a case study of Ripple Carry Adder and Carry-Skip Adder circuits. We design a low-overhead 2T1MTJ buffer and place it in the intermediate non-cri...

Resilience-Driven STT-RAM Cache Architecture for Approximate Computing

High-end manycore microprocessors exhibit large-sized caches (32MB – 128MB) that consume a significant amount of total energy. These caches are typically composed of 6T-SRAM cells, which lack efficiency in terms of area and leakage power [1][2]. The emerging memory technologies, like Spin-Transfer Torque RAM (STT-RAM), not only incur reduced leakage power but also provide high integration densi...

Optimal and Heuristic Global Code Motion for Minimal Spilling

The interaction of register allocation and instruction scheduling is a well-studied problem: Certain ways of arranging instructions within basic blocks reduce overlaps of live ranges, leading to the insertion of less costly spill code. However, there is little previous research on the extension of this problem to global code motion, i .e., the motion of instructions between blocks. We present a...